www.logiccircuit.org

Hello to all,
and thanks for my admission in the forum!

I tried some flipflops-circuits and with my J-Ks I fail.
(Please look on the screenshot)

On the upper one:
J = 1, K = 0 -> Set Q;
J = 0, K = 1 ->Reset Q;
J = 0, K = 0 -> save last output
J =1, K = 1 -> a alertbox with "Signalverlauf" (I'm using german) i.e. signal behavior (I think)

In the lower circuit:
J = 1, K = 0 -> Set Q;
J = 0, K = 1 ->Reset Q;
J = 0, K = 0 -> save last output
J =1, K = 1 -> both Q and /Q are set.

Whats my mistake(s)?
Who can help?

Have a nice day!

Fomtom

Hi Fomtom,
Welcome to the forum.
I guess you will need to crossover the wires from your Nor gates going back to And gates. So the wire from the top Nor should go to the bottom And and from the bottom Nor the top And.
Please see the this page for the reference: https://www.electronics-tutorials.ws/se ... seq_2.html
Regards,
Eugene

Hi admin,
I read the link bevore and some more literature to this theme (and I have some practice ).

As you know, there are two types of J-K-FF: With NORs (upper one) or wirh NANDs (lower one).
Both are build, like their theoretical (!) funktion without a clock-signal.

I think, this missing edge-up-clock is the problem.

Is there a possibility to build a clock-input sensoring to rising edge?
In practice I would take some inverters (throughput time for a standard ttl ca. 9ns) and "AND" the output of the series of the inverters to the original signal. So I have a short spice on rising edge.
Do logcircuit simulate a throughput time for the standard gates?

Thanks for your reaction and your tip!

Fomtom

There is no time simulation, but the circuits are evaluated in the order you expect. so you can build an edge detection.
As an example look at this topic: https://logiccircuit.org/forum/viewtopic.php?f=3&t=3