Yet another RISC CPU

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mcostalba
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Joined: Fri Jun 19, 2015 10:46 pm

Yet another RISC CPU

Post by mcostalba »

I have downloaded your very nice simulator few weeks ago and I had fun writing some stuff that I'd like to share for interested people.

It is a very simple CPU, harvard style, 8 bit registers (4 registers with r0 set at zero) and 16 bit instructions, all instructions execute in 2 cycles. The most noteworthy hardware feature is a barrel shifter that operates in 1 cycle for any lenght of shift /rotate, both from register or from an immediate value.

I have in paralel written a very simple assembly, with some alias to easy programming. I have used google spreadsheet, with the assemply itself as a javascript function (as required by google spreadsheet). Document is here:

https://docs.google.com/spreadsheets/d/ ... sp=sharing

The progam implements an 8 bit multipier in software (terms 'a' and 'b' are in m[0] and m[1] respectively, result in m[2], m[3])
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mcostalba
Posts: 5
Joined: Fri Jun 19, 2015 10:46 pm

Re: Yet another RISC CPU

Post by mcostalba »

Here are the real instructions implemented in the CPU:

Code: Select all

ld, st   ->   Load / Store indirect through register and offset e.g. ld r2, r1, 5  (r2 = Mem[r1 + 5])

add, sub, and, or, xor, shl, shr, rol, ror -> 3 registers ALU op e.g.  add r1, r2, r3 (r1 = r2 + r3)

add, and, or, xor -> immediate ALU op e.g. add r1, 5 (r1 = r1 + 5)

shl, shr, rol, ror -> shift with 2 registers and immediate e.g. shl r1, r2, 4 (r1 = r2 << 4)

beq, bne, bcs, bcc -> branch instructions with ofset e.g. bcc loop (branch if carry clear to loop)

addi -> add immediate e.g. addi r2, r1, 4  (r2 = r1 + 4), this is used for 'mov' instruction, see later

test -> test bit and set 'zero' flag, e.g. test r1, $80  (r1 & 0x80, test bit 7)

Here are the alias, instructions supported by assembler for easy programming and transformed on the base instructions (typically leveraging r0 is always set to zero):

Code: Select all

ld, st  from address e.g  ld r1, 4 equivalent to ld r1, r0, 4

mov from register e.g. mov r1, r2 (r1 = r2) equivalent to add r1, r0,r2

mov from immediate e.g. mov r1, $F (r1 = 15) equivalent to addi r1, r0, 15

not e.g not r2 equivalent to xor r2, r2, $FF

clr clear e.g. clr r1 (r1 = 0) equivalent to and r1, r1, 0

inc, dec  e.g. inc r3 equivalent to add r3, r3, 1

cmp compare e.g. cmp r1, r2 (sub r0, r1, r2) and cmp r1, 5 equivalent to addi r0, r1, 256 - 5 (two's complement)

sub with immediate, e.g. sub r2, 8 equivalent to add r2, 256 - 8 (two's complement)

shift instructions with immediate e.g. rol r1, 2 equivalent to rol r1, r1, 2
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admin
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Re: Yet another RISC CPU

Post by admin »

I like your assembler in spreadsheet. I guess you can add some of user interaction elements to make it more appealing. For example, display is very much like memory but it shows it content to user. Therefore, you can write a program that draw a rectangle.
By the way, there is a more traditional macro assembler, where you can define your instructions in it. You can try it: https://bitbucket.org/EugeneLepekhin/fusion/downloads you will need to download Fusion.zip file. There is a documentation file there.
mcostalba
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Joined: Fri Jun 19, 2015 10:46 pm

Re: Yet another RISC CPU

Post by mcostalba »

admin wrote: By the way, there is a more traditional macro assembler, where you can define your instructions in it. You can try it: https://bitbucket.org/EugeneLepekhin/fusion/downloads you will need to download Fusion.zip file. There is a documentation file there.
Thanks, I will give it a try.

BTW, speaking of assembler, currently I copy-paste assembled machine code in a txt file, then I use a small tool I have written myself to create a binary file (i.e. convert machine codes from ASCII to binary form) because ROM element can read just a binary file. I think it would be great and much more usable if ROM element could access an ASICII file and convert hex numbers strings to integers by itself. So that we can get rid of ad-hoc tools.

Always regarding ROM element, it would be nice if it could reload file content at startup, so to avoid manually opening dialog box and pick the file, everytime file changes.

Sorry for so many requests :-)

....btw, you have written a great tool, and it is also very stable!
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admin
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Re: Yet another RISC CPU

Post by admin »

Good ideas, thanks. I will try to implement them.
wolstenc
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Joined: Mon Jul 13, 2015 5:21 am

Re: Yet another RISC CPU

Post by wolstenc »

This is very impressive thank so you much.

I was playing around with your example program and may have accidentally edited it on google docs as I think it was set up for public editing. Apologies if I have.

Do you have any other examples?
mcostalba
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Joined: Fri Jun 19, 2015 10:46 pm

Re: Yet another RISC CPU

Post by mcostalba »

Yes, I allow public editing for people to have some fun with it.

I have no more software examples, I have switched to implement a hardware multiplier (radix 4 booth), I have almost finished it, then stopeed due to no free time. But if people is interested I can post it.
Hans Cadans
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Joined: Thu Apr 24, 2014 12:30 pm

Re: Yet another RISC CPU

Post by Hans Cadans »

Hi, mcostalba.

I've sent you some Private Mails.
Please, can you answer them

Best regards
Hans Cadans
mcostalba
Posts: 5
Joined: Fri Jun 19, 2015 10:46 pm

Re: Yet another RISC CPU

Post by mcostalba »

Hi Hans. I have replied in pm.
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